The present invention relates to a semiconductor memory and method for manufacturing the same and particularly to a large scale integrated semiconductor memory and method for manufacturing the same suitable for employment of optical lithography method.
Integration degree of a semiconductor memory is now in the age of 1 Mbits and a 4 Mbits memory is also under the development. Improvement in integration degree has been supported mainly by an ultraminiaturized pattern formation technology, namely the lithography and etching techniques. Therefore, it is very important to acquire the throughput as the lithography technology. For this reason, a reduction projection lithography using optical lenses has been widely employed as a method to form an ultraminiaturized pattern with comparatively high throughput. However, this reduction projection lithography provides a problem that when resolution of lens increases, depth of focus becomes shallow because the light is used and resolution is deteriorated if the surface which becomes the focusing surface (substrate surface) is not flat. The optical lithography is explained in the "VLSI Device Handbook", P139 to 141, issued on Nov. 28, 1983, by Science Forum Co., Ltd.
Meanwhile, element structure is concerned, it is more complicated and level difference formed on the substrate becomes large. It is because, for example, in the case of DRAM (Dynamic Random Access Memory), a capacitor having a capacitance value larger than the specified value must be formed as a measure for soft error to the .alpha.-ray and thereby a stacked capacitor, etc. is used to form a capacitor having a large capacity within a narrow region. (A cell structure using such capacitor is called a stacked capacitor type memory cell (STC memory cell).) This STC memory cell is disclosed in the Published Japanese Pat. No. 61-55258.
As explained above, in the reduction projection lithography technology to form an ultraminiaturized pattern, the substrate surface must be formed flat because the depth of focus is shallow. However, in actual, since there is a large level difference on the substrate as described above, focusing goes out of the depth of focus, resulting in a problem that pattern resolution is deteriorated or size accuracy is lowered.
In order to solve such problems as pattern resolution fault or drop of size accuracy resulting from the level difference on the substrate, a multilayer resist method has been proposed. This multilayer resist method is disclosed, for example, in the Japanese Laid-open Pat. No. 51-107775. In the case of this method, a flat surface which is not almost effectuated by level difference of substrate is formed with a thick organic film (BL: Bottom Layer) on the substrate having the level difference. Moreover, a shielding layer and a mask layer are sequentially formed thereon, the mask layer is patterned at the upper most layer by the photolitography technology and the shielding layer is etched with the patterned mask layer used as the mask. In addition, with this shielding layer used as the mask, the organic film as the lowest layer is etched by the anisotropic etching such as the sputter etching or ion beam etching, and the layer to be processed is etched with such organic film of the lowest layer used as the mask. Here, a substrate includes a single crystal silicon substrate and insulation film and conductive layer, etc. formed on the surface thereof.